HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 719

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The procedure for transmitting data sequentially, synchronized with ICDR (ICDRT) write
operations, is described below.
[1] Perform initial settings as described in section 16.4.2, Initial Setting.
[2] Read the BBSY flag in ICCR to confirm that the bus is free.
[3] Set bits MST and TSR in ICCR to 1 to switch to the master transmit mode.
[4] Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is
[5] The IRIC and IRTR flags are set to 1 when the start condition is generated. If the IEIC bit in
[6] After the start condition is detected, write the data (slave address + R/W) to ICDR. With the
[7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
[8] Read the ACKB bit in ICSR to confirm that its value is 0. If the slave device has not returned
[9] Write the transmit data to ICDR. Next, clear the IRIC flag to 0 to indicate the end of the
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
[11] Read the ACKB bit in ICSR to confirm that the slave device has returned an acknowledge
[12] Clear the IRIC flag to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to
high, and generates the start condition.
ICCR has been set to 1, an interrupt request is sent to the CPU.
I
following the start condition indicates the 7-bit slave address and transmit/receive direction
(R/W). Next, clear the IRIC flag to 0 to indicate the end of the transfer. Continue successively
writing to ICDR and clearing the IRIC flag to ensure that processing of other interrupts does
not intervene. If the time required to transmit one byte of data elapses by the time the IRIC
flag is cleared, it will not be possible to determine the end of the transmission. The master
device sequentially sends the transmit clock and the data written to ICDR using the timing
shown in figure 16.8. The selected slave device (i.e., the slave device with the matching slave
address) drives SDA low at the 9th transmit clock pulse and returns an acknowledge signal.
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
an acknowledge signal and the value of ACKB is 1, perform the transmit end processing
described in step [12] and then recommence the transmit operation from the beginning.
transfer. Then continue successively writing to ICDR and clearing the IRIC flag as described
in step [6]. Transmission of the next frame is synchronized with the internal clock.
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
signal and the value of ACKB is 0. If the slave device has not returned an acknowledge signal
and the value of ACKB is 1, perform the transmit end processing described in step [12].
high when SCL is high, and generates the stop condition.
2
C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame data
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 657 of 982
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600