HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 593

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

3. When the first data is received, the RxRDY flag is set to 1. A DTC transfer request by IERxI
4. Similarly, the data field reception and load are repeated.
5. When the last data is received, the DTC completes the data transfer for the specified number of
6. When the DTC transfer has been completed, an RxRDY interrupt (IERxI) is issued to the
7. When the last data is received, a receive normal completion (RxF) interrupt (IERSI) occurs. In
Notes: 1. As a receive status interrupt (IERSI), the receive error termination (RxE) interrupt as
occurs, and the DTC loads data from the IEBus receive buffer register (IERBR) and clears the
RxRDY flag.
bytes after loading the receive data to the RAM. In this case, the DTC does not clear the
RxRDY flag. It, however, clears the DTC enable register G (DTCEG). Accordingly, hereafter,
no transfer request will be issued to the DTC.
CPU. In this interrupt handling routine, the RxRDY flag is cleared.
this case, the CPU clears the RxF flag in order to complete the normal completion interrupt.
The SRE flag is cleared to 0.
2. The interrupt occurs after the DTC transfer has been completed. Accordingly, the
well as the receive start detection (RxS) and receive normal completion (RxF)
interrupts must be enabled. If an error termination interrupt is disabled, no interrupt is
generated even if the reception is terminated by an error.
interrupt described in item 6 actually occurs after item 7 above.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 531 of 982
REJ09B0054-0600