HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 679

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

15.7.7
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mode. Figure 15.32 illustrates the retransfer operation when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1,
Figure 15.33 shows a flowchart for reception. A sequence of receive operations can be performed
automatically by specifying the DTC to be activated using an RXI interrupt source. In a receive
operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI
request is designated beforehand as a DTC activation source, the DTC will be activated by the
RXI request, and the receive data will be transferred. At this moment, if DISEL in DTC is 0 with
the transfer counter not being 0, the RDRF flag is automatically cleared. When DISEL is 1, or
DISEL is 0 with the transfer counter being 0, the DTC transfers receive data but does not clear the
flag. Therefore, the flag should be cleared by CPU. If an error occurs in receive mode and the
ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. Hence, so
the error flag must be cleared to 0. In the event of an error, the DTC is not activated and receive
data is skipped. Therefore, receive data is transferred for only the specified number of bytes in the
event of an error. Even when a parity error occurs in receive mode and the PER flag is set to 1, the
data that has been received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, refer to section 15.4, Operation in
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
the receive operation is judged to have been completed normally, and the RDRF flag in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is
generated.
Asynchronous Mode.
RDRF
PER
Serial Data Reception (Except for Block Transfer Mode)
Ds
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Figure 15.32 Retransfer Operation in SCI Receive Mode
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Section 15 Serial Communication Interface (SCI)
Retransferred frame
Rev. 6.00 Mar. 18, 2010 Page 617 of 982
(DE)
Ds D0 D1 D2 D3 D4
Transfer
frame n+1st
REJ09B0054-0600