HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 860

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 24 Power-Down Modes
24.8
24.8.1
When the SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in
LPWRCR = 1, and the PSS bit in TCSR_1 (WDT_1) = 1 in subactive mode, CPU operation shifts
to subsleep mode.
In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0 to TMR3, WDT_0,
and WDT_1 and system clock oscillator are also stopped. The contents of the CPU’s internal
registers, the data in internal RAM, and the statuses of the internal peripheral modules (excluding
the SCI and the A/D converter) and I/O ports are retained.
24.8.2
• Subsleep mode is exited by an interrupt (interrupts from internal peripheral modules, NMI pin,
• Exiting Subsleep Mode by Interrupts
• Exiting Subsleep Mode by RES Pin or MRES Pin
• Exiting Subsleep Mode by STBY Pin
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or IRQ7 to IRQ0), or signals at the RES or STBY pin.
When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts.
In the case of IRQ7 to IRQ0 interrupts, subsleep mode is not cancelled if the corresponding
enable bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from
the internal peripheral modules, the interrupt enable register has been set to disable the
reception of that interrupt, or is masked by the CPU.
For exiting subsleep mode by the RES or MRES pin, see section 24.4.2, Clearing Software
Standby Mode.
When the STBY pin or MRES pin level is driven low, a transition is made to hardware standby
mode.
Subsleep Mode
Transition to Subsleep Mode
Exiting Subsleep Mode