HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 456

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 6.00 Mar. 18, 2010 Page 394 of 982
REJ09B0054-0600
Bit
3
2
Bit Name
TGFD
TGFC
Initial value
0
0
R/W
R/(W) *
R/(W) *
1
1
Description
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and
3 *
In channels 1, 2, 4 *
always read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and
3 *
In channels 1, 2, 4 *
always read as 0 and cannot be modified.
[Setting conditions]
•
•
[Clearing conditions]
•
•
3
3
.
.
When TCNT = TGRD while TGRD is functioning
as output compare register
When TCNT value is transferred to TGRD by
input capture signal while TGRD is functioning
as input capture register
When DTC is activated by TGID interrupt while
DISEL bit of MRB in DTC is 0 with the transfer
counter not being 0
When 0 is written to TGFD after reading TGFD
= 1
When TCNT = TGRC while TGRC is functioning
as output compare register
When TCNT value is transferred to TGRC by
input capture signal while TGRC is functioning
as input capture register
When DTC is activated by TGIC interrupt while
DISEL bit of MRB in DTC is 0 with the transfer
counter not being 0
When 0 is written to TGFC after reading TGFC
= 1
3
3
, and 5 *
, and 5 *
3
3
, bit 3 is reserved. It is
, bit 2 is reserved. It is