HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 653

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Figure 15.10 shows a sample flowchart for data transmission.
and clear TDRE flag in SSR to 0
Write transmit data to TDR
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Clear DR to 0 and
Start transmission
Break output?
set DDR to 1
Initialization
Figure 15.10 Sample Serial Transmission Flowchart
TDRE = 1
TEND = 1
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
Section 15 Serial Communication Interface (SCI)
Notes: 1. Supported only by the H8S/2239
Rev. 6.00 Mar. 18, 2010 Page 591 of 982
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
[4] Break output at the end of serial
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DMAC *
the DTC *
transmit-data-empty interrupt (TXI)
request, and data is written to TDR.
transmission:
To output a break in serial
transmission, set DR for the port
corresponding to the TxD pin to 0,
clear DDR to 1, then clear the TE
bit in SCR to 0.
2. The case, in which the DTC
Group.
automatically checks and clears
the TDRE flag, occurs only when
DISEL in DTC is 0 with the
transfer counter not being 0.
Therefore, the TDRE flag should
be cleared by CPU when DISEL
is 1, or when DISEL is 0 with the
transfer counter being 0.
2
is activated by a
REJ09B0054-0600
1
or