HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 291

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

8.3.6
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 8.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
Bit
7 to 4
3
2
1
0
DMA Write Enable Register (DMAWER)
Bit Name
⎯
WE1B
WE1A
WE0B
WE0A
Initial Value
All 0
0
0
0
0
R/W
−
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Write Enable 1B
Enables or disables writes to all bits in
DMACR1B, bits 11, 7, and 3 in DMABCR, and
bit 5 in DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 1A
Enables or disables writes to all bits in
DMACR1A, and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0B
Enables or disables writes to all bits in
DMACR0B, bits 9, 5, and 1 in DMABCR, and bit
4 in DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0A
Enables or disables writes to all bits in
DMACR0A, and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Rev. 6.00 Mar. 18, 2010 Page 229 of 982
Section 8 DMA Controller (DMAC)
REJ09B0054-0600