HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 181

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

4.1
As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Trap instruction exception
handling requests are accepted at all times in program execution state.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode set by the INTM1 and INTM0 bits in SYSCR.
Table 4.1
Priority
High
4.2
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses.
Low
Exception Handling Types and Priority
Exception Sources and Exception Vector Table
Exception Type
Reset
Trace
Interrupt
Trap instruction
(TRAPA)
Exception Types and Priority
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES
or MRES pin, or when the watchdog timer overflows. The
CPU enters the power-on reset state when the RES pin is
low. The CPU enters the manual reset state when the
MRES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
Traces are enabled only in interrupt control mode 2. Trace
exception handling is not executed after execution of an
RTE instruction.
handling ends, if an interrupt request has been issued.
Interrupt detection is not performed on completion of ANDC,
ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
Starts when execution of the current instruction or exception
Started by execution of a trap instruction (TRAPA). Trap
instruction exception handling requests are accepted at all
times in program execution state.
Rev. 6.00 Mar. 18, 2010 Page 119 of 982
Section 4 Exception Handling
REJ09B0054-0600