HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 715

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.3.8
DDCSWR controls the I
clear.
Bit
7 to 4 ⎯
3
2
1
0
Legend:
×:
Note:
16.4
The I
16.4.1
The I
following a start condition always consists of 8 bits. The I
The clocked synchronous serial format is a non-addressing format with no acknowledge bit. This
is shown in figure 16.4. Figure 16.5 shows the I
2
2
C bus interface has serial and I
C bus formats are addressing formats and an acknowledge bit is inserted. The first frame
Bit Name
CLR3
CLR2
CLR1
CLR0
Don’t care
* Only 0 can be written to these bits, to clear the flag.
Operation
DDC Switch Register (DDCSWR)
I
2
C Bus Data Format
Initial
Value
All 0
1
1
1
1
2
C bus interface format automatic switching function and internal latch
R/W
R/(W) * Reserved
W
W
W
W
2
C bus formats.
Description
The write value should always be 0.
I
When bits CLR3 to CLR0 are set, a clear signal is generated
for the I
state is initialized. The write data for these bits is not retained.
To perform I
to simultaneously using an MOV instruction. Do not use a bit
manipulation instruction such as BCLR.
00××: Setting prohibited
0100: Setting prohibited
0101: IIC_0 internal latch cleared
0110: IIC_1 internal Iatch cleared
0111: IIC_0, IIC_1 internal Iatch cleared
1×××: Invalid setting
2
C Bus Interface Clear 3 to 0
2
C bus interface internal latch circuit, and the internal
2
C bus timing.
2
C clearance, bits CLR3 to CLR0 must be written
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 653 of 982
2
C bus format is shown in figure 16.3.
2
C Bus Interface (IIC) (Option)
REJ09B0054-0600