HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 214

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 5 Interrupt Controller
(1) Interrupt Source Selection
The DMAC* startup sources are directly input to each channel. The startup source for each
DMAC* channel is selected by the DMACR DTF3 to DTF0 bits. Whether or not the selected
startup source is managed by the DMAC* can be selected with the DMABCR DTA bit. If the
DTA bit is set to 1, the interrupt source that has become the DMAC* startup source will not be
either a DTC startup source or a CPU interrupt source.
Interrupt sources other than the interrupt managed by the DMAC* are selected to be DTC startup
sources or CPU interrupt requests by the DTC DTCERA to DTCERF DTCE bits.
After a DTC data transfer, a CPU interrupt can be requested by clearing the DTCE bit to 0 by
specifying that with the DTC MRB DISEL bit.
Note that when the DTC has performed the stipulated number of data transfers and the transfer
counter has become 0, the DTCE bit can be cleared to 0 and a CPU interrupt can be requested.
Note: * Supported only by the H8S/2239 Group.
Rev. 6.00 Mar. 18, 2010 Page 152 of 982
REJ09B0054-0600
peripheral
interrupt
modules
Note: * Supported only by the H8S/2239 Group.
function
Internal
IRQ
Interrupt source
clear signal
Interrupt request
Figure 5.8 DTC and DMAC* Interrupt Control
Interrupt controller
Selection
DTVECR
DTCER
circuit
Selection
signal
SWDTE
clear signal
Clear
signal
DMAC*
Determination of
Control logic
priority
CPU interrupt
request vector
number
DTC start
request vector
number
Clear signal
I, I2 to I0
DTC
CPU