HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 739

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Table 16.7 I
Notes: 1. Not supported by the H8S/2258 Group.
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
5. The I
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition
output setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave) *
Data output setup time (slave) *
Data output hold time
therefore depends on the system clock cycle t
and table 27.34 (H8S/2238B and H8S/2236B). Note that the I
specifications will not be met with a system clock frequency of less than 5 MHz.
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table in
table 16.8.
2. Supported only by the H8S/2258 Group.
3. 6 t
2
C bus interface specification for the SCL rise time t
cyc
2
C Bus Timing (SCL and SDA Output)
when IICX is 0, 12 t
1
2
cyc
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
when IICX is 1.
2
C bus interface monitors the SCL line and synchronizes
sr
(the time for SCL to go from low to V
Output Timing
28 t
0.5 t
0.5 t
0.5 t
0.5 t
1 t
0.5 t
1 t
1 t
1 t
3 t
cyc
2
C bus interface, the high period of SCL is
, as shown in table 27.22 (H8S/2239 Group)
SCLO
SCLLO
SCLL
SCLL
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
– 3 t
– (6 t
to 256 t
– 3 t
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 677 of 982
– 1 t
– 1 t
+ 2 t
cyc
cyc
cyc
sr
cyc
cyc
cyc
or 12 t
cyc
is under 1000 ns (300 ns for high-
2
C bus interface AC timing
cyc
2
C Bus Interface (IIC) (Option)
) *
3
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REJ09B0054-0600
Notes
Figure 27.34
IH
) exceeds