HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 222

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 6 PC Break Controller (PBC)
Notes: 1. Only a 0 can be written to this bit to clear the flag.
6.2.4
BCRB is the channel B break control register. The bit configuration is the same as for BCRA.
6.3
The operation flow from break condition setting to PC break interrupt exception handling is
shown in section 6.3.1, PC Break Interrupt Due to Instruction Fetch, and section 6.3.2, PC Break
Interrupt Due to Data Access, taking the example of channel A.
6.3.1
1. Set the break address in BARA.
2. Set the break conditions in BCRA.
3. When the instruction at the set address is fetched, a PC break request is generated immediately
4. After priority determination by the interrupt controller, PC break interrupt exception handling
Rev. 6.00 Mar. 18, 2010 Page 160 of 982
REJ09B0054-0600
Bit
0
For a PC break caused by an instruction fetch, set the address of the first instruction byte as the
break address.
Set bit 6 (CDA) to 0 to select the CPU because the bus master must be the CPU for a PC break
caused by an instruction fetch. Set the address bits to be masked to bits 5 to 3 (BAMRA2 to 0).
Set bits 2 and 1 (CSELA1 and 0) to 00 to specify an instruction fetch as the break condition.
Set bit 0 (BIEA) to 1 to enable break interrupts.
before execution of the fetched instruction, and the condition match flag (CMFA) is set.
is started.
2. Read the state wherein CMFA = 1 twice or more, when the CMFA is polled after
3. Supported only by the H8S/2239 Group.
Bit Name
BIEA
Break Control Register B (BCRB)
Operation
PC Break Interrupt Due to Instruction Fetch
inhibiting the PC break interruption.
Initial Value
0
R/W
R/W
When this bit is 1, the PC break interrupt request
of channel A is enabled.
Description
Break Interrupt Enable