HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 469

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Example of Buffer Operation Setting Procedure: Figure 11.15 shows an example of the buffer
operation setting procedure.
Examples of Buffer Operation:
1. When TGR is an output compare register
Figure 11.16 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details on PWM modes, see section 11.4.5, PWM Modes.
Figure 11.15 Example of Buffer Operation Setting Procedure
Select TGR function
Set buffer operation
<Buffer operation>
Buffer operation
Start count
[1]
[2]
[3]
[1]
[2]
[3]
Designate TGR as an input capture register or
output compare register by means of TIOR.
Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set the CST bit in TSTR to 1 to start the count
operation.
Rev. 6.00 Mar. 18, 2010 Page 407 of 982
Section 11 16-Bit Timer Pulse Unit (TPU)
REJ09B0054-0600