HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 795

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

2. SCI should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area
6. Before branching to the programming control program, the chip terminates transfer operations
7. Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting
8. All interrupts are disabled during programming or erasing of the flash memory.
Note: * The input signals on the FWE and mode pins must satisfy the mode programming
In boot mode, if any data has been programmed into the flash memory (if all data is not 1), all
flash memory blocks are erased. Boot mode is for use when user program mode is unavailable,
such as the first time on-board programming is performed, or if the program activated in user
program mode is accidentally erased.
bit, and no parity.
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI bit rate to match that
of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host’s
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate
and system clock frequency of this LSI within the ranges listed in table 20.5.
H'FFC000 to H'FFDFFF is the area to which the programming control program is transferred
from the host. The boot program area cannot be used until the execution state in boot mode
switches to the programming control program.
by SCI (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer of
write data or verify data with the host. The TxD pin is high. The contents of the CPU general
registers are undefined immediately after branching to the programming control program.
These registers must be initialized at the beginning of the programming control program, as the
stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
the FWE pin and mode pins, and executing reset release*. Boot mode is also cleared when a
WDT overflow occurs.
setup time (t
MDS
= 200 ns) at the reset release timing.
Section 20 Flash Memory (F-ZTAT Version)
Rev. 6.00 Mar. 18, 2010 Page 733 of 982
REJ09B0054-0600