HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 558

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Note that locking and unlocking are not performed in broadcast communications.
Note: * There are three methods to unlock by a locked unit itself.
14.1.4
Figure 14.5 shows the bit format (conceptual diagram) configuring the IEBus communications
frame.
Each period of bit format for use of active high signals is described below.
• Preparation period: first logic 1 period (high level)
• Synchronous period: subsequent logic 0 period (low level)
• Data period: period indicating bit value (logic 1: high level, logic 0: low level)
• Halt period: last logic 1 cycle (high level)
For use of active low signals, levels are reversed from the active high signals.
The synchronous and data periods have approximately the same length.
The IEBus is synchronized bit by bit. The specifications for the time of all bits and the periods
allocated to the bits differ depending on the type of transfer bits and the unit (master or slave unit).
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REJ09B0054-0600
in a single communications frame, the slave unit is unlocked by the master unit. In this case, a
bit (bit 2) relevant to lock in the byte indicating the slave status is cleared to 0.
Bit Format
• Perform hardware reset
• Enter module stop mode
• Issue unlock command by the IEBus command register (IECMR)
Note that the LCK flag in IEFLG can be used to check whether the unit is
locked/unlocked.
Logic 1
Logic 0
Figure 14.5 IEBus Bit Format (Conceptual Diagram)
Active low: Logic 1 = low level and logic 0 = high level
Active high: Logic 1 = high level and logic 0 = low level
Preparation
period
Synchronous
period
period
Data
period
Halt