HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 772

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 18 D/A Converter
18.4
Two channels of the D/A converter can perform conversion individually.
When the DAOE bit in DACR is set to 1, D/A conversion is enabled and the conversion results are
output.
An example of D/A conversion of channel 0 is shown below. The operation timing is shown in
figure 18.2.
1. Write conversion data to DADR0.
2. When the DAOE0 bit in DACR is set to 1, D/A conversion starts. After the interval of t
3. Conversion starts immediately after DADR0 is modified. After the interval of t
4. When the DAOE bit is cleared to 0, analog output is disabled.
Rev. 6.00 Mar. 18, 2010 Page 710 of 982
REJ09B0054-0600
the conversion results are output from the analog output pin DA0. The conversion results are
output continuously until DADR0 is modified or DAOE0 bit is cleared to 0. The output value
is calculated by the following formula:
(DADR contents) / 256 × Vref
conversion results are output.
Legend:
t
DCONV
φ
Address
DADR0
DAOE0
DA0
Operation
: D/A conversion time
DADR0
write cycle
High impedance state
Figure 18.2 D/A Converter Operation Example
DACR
write cycle
Conversion data (1)
t
DCONV
Conversion result (1)
DADR0
write cycle
t
DCONV
Conversion data (2)
Conversion result (2)
DACR
write cycle
DCONV
,
DCONV
,

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