HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 832

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 23 Clock Pulse Generator
Note:
23.2
System clock pulses can be supplied by connecting a crystal resonator, or by input of an external
clock.
23.2.1
A crystal resonator can be connected as shown in the example in figure 23.2. Select the damping
resistance R
Rev. 6.00 Mar. 18, 2010 Page 770 of 982
REJ09B0054-0600
Bit
1
0
Bit Name
STC1
STC0
* When watch mode or subactive mode is entered, set high-speed mode.
System Clock Oscillator
Connecting a Crystal Resonator
Note: C
d
according to table 23.1. An AT-cut parallel-resonance crystal should be used.
L1
Figure 23.2 Connection of Crystal Resonator (Example)
and C
Initial Value
0
0
EXTAL
XTAL
L2
are reference values including the floating capacitance of the board.
R
R/W
R/W
R/W
d
Description
Multiplication factor setting
Specifies multiplication factor of the PLL circuit built
in the evaluation chip. The specified multiplication
factor becomes valid software standby mode, watch
mode, or subactive mode is entered.
These bits should be set to 11 in this LSI. Since the
value becomes STC1 = STC0 = 0 after a reset, set
STC1 = STC0 = 1.
00: × 1
01: × 2 (setting prohibited)
10: × 4 (setting prohibited)
11: PLL is bypass
C
C
L1
L2
C
L1
= C
L2
= 10 to 22 pF

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