HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 32

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4 Operation .......................................................................................................................... 452
12.5 Operation Timing.............................................................................................................. 453
12.6 Operation with Cascaded Connection ............................................................................... 457
12.7 Interrupt Sources............................................................................................................... 458
12.8 Usage Notes ...................................................................................................................... 459
Section 13 Watchdog Timer (WDT) .................................................................465
13.1 Features............................................................................................................................. 465
13.2 Input/Output Pins .............................................................................................................. 467
13.3 Register Descriptions ........................................................................................................ 467
13.4 Operation .......................................................................................................................... 473
13.5 Interrupt Sources............................................................................................................... 476
13.6 Usage Notes ...................................................................................................................... 477
Rev. 6.00 Mar. 18, 2010 Page xxx of lx
REJ09B0054-0600
12.3.5 Timer Control/Status Register (TCSR)................................................................ 447
12.4.1 Pulse Output......................................................................................................... 452
12.5.1 TCNT Incrementation Timing ............................................................................. 453
12.5.2 Timing of CMFA and CMFB Setting when a Compare-Match Occurs .............. 454
12.5.3 Timing of Timer Output when a Compare-Match Occurs ................................... 455
12.5.4 Timing of Compare-Match Clear when a Compare-Match Occurs ..................... 455
12.5.5 TCNT External Reset Timing .............................................................................. 456
12.5.6 Timing of Overflow Flag (OVF) Setting ............................................................. 456
12.6.1 16-Bit Count Mode .............................................................................................. 457
12.6.2 Compare-Match Count Mode .............................................................................. 457
12.7.1 Interrupt Sources and DTC Activation ................................................................ 458
12.7.2 A/D Converter Activation.................................................................................... 458
12.8.1 Contention between TCNT Write and Clear........................................................ 459
12.8.2 Contention between TCNT Write and Increment ................................................ 459
12.8.3 Contention between TCOR Write and Compare-Match ...................................... 460
12.8.4 Contention between Compare-Matches A and B................................................. 461
12.8.5 Switching of Internal Clocks and TCNT Operation............................................. 461
12.8.6 Contention between Interrupts and Module Stop Mode ...................................... 463
12.8.7 Mode Setting of Cascaded Connection ................................................................ 463
13.3.1 Timer Counter (TCNT)........................................................................................ 468
13.3.2 Timer Control/Status Register (TCSR)................................................................ 468
13.3.3 Reset Control/Status Register (RSTCSR) (only WDT_0) ................................... 472
13.4.1 Watchdog Timer Mode ........................................................................................ 473
13.4.2 Interval Timer Mode............................................................................................ 474
13.4.3 Timing of Setting Overflow Flag (OVF) ............................................................. 475
13.4.4 Timing of Setting Watchdog Timer Overflow Flag (WOVF) ............................. 476
13.6.1 Notes on Register Access..................................................................................... 477