HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 561

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit
5
4
3
Bit Name
DEE
CKS
RE
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Broadcast Receive Error Interrupt Enable
Since the acknowledgement is not returned between the
master and slave units in broadcast reception, the master
unit cannot decide whether the slave unit is in the receive
enabled state. If this bit is set to 1, a reception error
interrupt occurs (note that there is not the corresponding bit
in the IEBus receive error flag register to this error) when
the receive buffer is not in the receive enabled state during
receiving the control field in broadcast reception (when the
RE bit is not set to 1 or the RxRDY flag is set.). At this time,
the master address is stored in IEMA1 and IEMA2. The
receive data is not stored in the IERCTL.
While this bit is 0, a reception error interrupt does not occur
when the receive buffer is not in the receive enabled state,
and the reception stops and enters the wait state. The
master address is not saved.
0: A broadcast receive error is not generated up to the
1: A broadcast receive error is generated up to the control
Input Clock Select
Always set this bit to 0 in this LSI. Selects clock used by
the IEB.
Receive Enable
Enables/disables IEB reception. This bit must be set at the
initial setting before frame reception. Changing this bit
before receiving the control field is valid, however,
changing this bit after receiving the control field is invalid
and the value before the change is validated.
0: Reception is disabled.
1: Reception is enabled.
control field.
field.
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
Rev. 6.00 Mar. 18, 2010 Page 499 of 982
REJ09B0054-0600