HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 841

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

23.3
The duty adjustment circuit is valid when oscillation frequency is more than 5 MHz. The duty
adjustment circuit adjusts clock output fr/m the system clock oscillator to generate the system
clock (φ).
23.4
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
23.5
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from system clock (φ), or
medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).
23.6
When using the IEBus, the system clock must be set to either 12 MHz or 12.58 MHz. When the
IEBus is not used, the system clock can be set to an arbitrary frequency between 10 MHz to 13.5
MHz.
Note: IEBus is supported only by the H8S/2258 Group.
Duty Adjustment Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit
System Clock when Using IEBus
Rev. 6.00 Mar. 18, 2010 Page 779 of 982
Section 23 Clock Pulse Generator
REJ09B0054-0600