HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 754

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 17 A/D Converter
17.3
The A/D converter has the following registers. For details on the module stop control register,
refer to section 24.1.2, Module Stop Control Registers A to C (MSTPCRA to MSTPCRC).
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
17.3.1
There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown
in table 17.2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. Therefore,
when reading the ADDR, read only the upper byte, or read in word unit.
Table 17.2 Analog Input Channels and Corresponding ADDR Registers
Rev. 6.00 Mar. 18, 2010 Page 692 of 982
REJ09B0054-0600
Group 0 (CH2 = 0)
AN0
AN1
AN2
AN3
A/D Data Registers A to D (ADDRA to ADDRD)
Register Descriptions
Analog Input Channel
Group 1 (CH2 = 1)
AN4
AN5
AN6
AN7
A/D Data Register to be Stored the Results of
A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD