HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 244

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 7 Bus Controller
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
7.6.2
Table 7.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 7.3
Notes: Hi-Z:
Rev. 6.00 Mar. 18, 2010 Page 182 of 982
REJ09B0054-0600
Area
8-bit access
space
16-bit
access
space
Invalid: Input state; input value is ignored.
Figure 7.9 Access Sizes and Data Alignment Control (16-Bit Access Space)
Valid Strobes
Data Buses Used and Valid Strobes
Access
Size
Byte
Byte
Word
Byte size
Byte size
Word size
Longword
size
High impedance.
Read/
Write
Read
Write
Read
Write
Read
Write
• Even address
• Odd address
1st bus cycle
2nd bus cycle
Address
—
—
Even
Odd
Even
Odd
—
—
Valid Strobe
RD
HWR
RD
HWR
LWR
RD
HWR, LWR
D15
Upper data bus
Upper Data Bus
(D15 to D8)
Valid
Valid
Invalid
Valid
Hi-Z
Valid
Valid
D8 D7
Lower data bus
D0
Lower Data Bus
(D7 to D0)
Invalid
Hi-Z
Invalid
Valid
Hi-Z
Valid
Valid
Valid