HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 223

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.3.2
1. Set the break address in BARA.
2. Set the break conditions in BCRA.
3. After execution of the instruction that performs a data access on the set address, a PC break
4. After priority determination by the interrupt controller, PC break interrupt exception handling
6.3.3
• When a PC break interrupt is generated at the transfer address of an EEPMOV.B instruction
• When a PC break interrupt is generated at a DTC transfer address
6.3.4
The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
• When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
• When the SLEEP instruction causes a transition from high speed mode to subactive mode
• When the SLEEP instruction causes a transition from subactive mode to high speed (medium
For a PC break caused by a data access, set the target ROM, RAM, I/O, or external address
space address as the break address. Stack operations and branch address reads are included in
data accesses.
Select the bus master with bit 6 (CDA). Set the address bits to be masked to bits 5 to 3
(BAMRA2 to 0). Set bits 2 and 1 (CSELA1 and 0) to 01, 10, or 11 to specify data access as the
break condition. Set bit 0 (BIEA) to 1 to enable break interrupts.
request is generated and the condition match flag (CMFA) is set.
is started.
PC break exception handling is executed after all data transfers have been completed and the
EEPMOV.B instruction has ended.
PC break exception handling is executed after the DTC has completed the specified number of
data transfers, or after data for which the DISEL bit is set to 1 has been transferred.
sleep mode, or from subactive mode to subsleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode, and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6.2 (A)).
(figure 6.2 (B)).
speed) mode (figure 6.2 (C)).
Notes on PC Break Interrupt Handling
PC Break Interrupt Due to Data Access
Operation in Transitions to Power-Down Modes
Rev. 6.00 Mar. 18, 2010 Page 161 of 982
Section 6 PC Break Controller (PBC)
REJ09B0054-0600