HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 607

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

14.6.7
When transmit or receive data is transferred by the DTC, bit 5 (for transmission) or bit 6 (for
reception) in DTCERG must be set by the bit manipulation instruction (such as BSET or BCLR).
In this case, other bits (bits 7 and 4 to 0) in DTCERG must not be set to 1.
14.6.8
Figure 14.15 shows the operation when a timing error occurs.
When a timing error occurs in data transmission (1), there is a possibility that the next data is
already transferred to the transmit buffer by the DTC and the TxRDY flag that is the DTC
initiation source is already cleared to 0 (2).
In this case, if retransfer is performed, data remained in the transmit buffer (previous frame data)
is transmitted as the first byte data of the data field (3).
To avoid this error, in master transmission, the first byte data in the data field should be written to
the transmit buffer by software instead of using the DTC. After that, data can be transferred by the
DTC. In this case, the SAR (transfer source address) and CRA (transfer counter) should be
specified as follows.
• An address of the on-chip memory that stores the second byte data → SAR
• The number of bytes specified by message length –1 → CRA
TxRDY
IETSR
IETEF
Legend:
S:
MA:
SA:
CF:
LF:
D1, D2, ...Dn-1, Dn: Data field
TTME
Notes on DTC Specification
Error Handling in Transmission
Start bit, broadcast bit
Master address field
Slave address field
Control field
Message length field
S
Figure 14.15 Error Processing in Transfer
MA
Transmit error frame
1st byte data
transferred
by DTC
SA
CF
LF
2nd byte data
transferred
by DTC
(2)
Section 14 IEBus™ Controller (IEB) [H8S/2258 Group]
D1
(1)
Timing error
Rev. 6.00 Mar. 18, 2010 Page 545 of 982
S
MA
Retransfer frame
SA
CF
LF
1st byte data
transferred
by DTC
REJ09B0054-0600
(3)
D2 D1