HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 229

MCU 3V 384K I-TEMP 100-TQFP

HD64F2239TF20I

Manufacturer Part Number
HD64F2239TF20I
Description
MCU 3V 384K I-TEMP 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2200r
Datasheet

Specifications of HD64F2239TF20I

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2239TF20I
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.2
Table 7.1 summarizes the pins of the bus controller.
Table 7.1
7.3
The following shows the registers of the bus controller.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register H (WCRH)
• Wait control register L (WCRL)
• Bus control register H (BCRH)
• Bus control register L (BCRL )
• Pin function control register (PFCR)
Name
Address strove
Read
High write
Low write
Chip select 7 to 0 CS7 to CS0
Wait
Bus request
Bus request
acknowledge
Input/Output Pins
Register Descriptions
Pin Configuration
Symbol
AS
RD
HWR
LWR
WAIT
BREQ
BACK
I/O
Output Strobe signal indicating that address output on
Output Strobe signal indicating that external space is being
Output Strobe signal indicating that external space is to be
Output Strobe signal indicating that external space is to be
Output Strobe signal indicating that areas 7 to 0 are selected.
Input
Input
Output Acknowledge signal indicating that bus has been
Function
address bus is enabled.
read.
written, and upper half (D15 to D8) of data bus is
enabled.
written, and lower half (D7 to D0) of data bus is
enabled.
Wait request signal when accessing external 3-state
access space.
Request signal that releases bus to external device.
released.
Rev. 6.00 Mar. 18, 2010 Page 167 of 982
Section 7 Bus Controller
REJ09B0054-0600

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