HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 460

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 11 16-Bit Timer Pulse Unit (TPU)
11.4
11.4.1
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Counter Operation: When one of bits CST2 to CST0 (H8S/2227 Group) or bits CST5 to CST0
(groups other than H8S/2227) in TSTR is set to 1, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
1. Example of count operation setting procedure
Rev. 6.00 Mar. 18, 2010 Page 398 of 982
REJ09B0054-0600
Figure 11.3 shows an example of the count operation setting procedure.
Select output compare register
Select counter clearing source
Basic Functions
Operation
Select counter clock
Operation selection
<Periodic counter>
Periodic counter
Start count
Set period
Figure 11.3 Example of Counter Operation Setting Procedure
[1]
[2]
[3]
[4]
[5]
<Free-running counter>
Free-running counter
Start count
[5]
[1]
[2]
[3]
[4]
[5]
Select the counter
clock with bits TPSC2
to TPSC0 in TCR. At
the same time, select
the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
For periodic counter
operation, select the
TGR to be used as the
TCNT clearing source
with bits CCLR2 to
CCLR0 in TCR.
Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
Set the periodic
counter cycle in the
TGR selected in [2].
Set the CST bit in
TSTR to 1 to start the
counter operation.