HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 722

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 660 of 982
REJ09B0054-0600
Figure 16.10 Flowchart for Master Receive Mode (Receiving Multiple Bytes) (WAIT = 1)
2
C Bus Interface (IIC) (Option)
No
No
No
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
Clear IRIC flag in ICCR
Clear IRIC flag in ICCR
Read IRIC flag in ICCR
1 clock cycle wait state
Set ACKB = 0 (ICSR)
Set WAIT = 1 (ICMR)
Set ACKB = 1 (ICSR)
Set WAIT = 0 (ICMR)
Master receive mode
and SCP = 0 (ICCR)
Set TRS = 0 (ICCR)
Set TRS = 1 (ICCR)
Write BBSY = 0
Last receive?
Read ICDR
Read ICDR
Read ICDR
Read ICDR
IRTR = 1?
IRTR = 1?
IRIC = 1?
IRIC = 1?
End
Yes
Yes
Yes
No
No
Yes
Yes
(Example)
[1] Set to receive mode.
[2] Receive start, dummy read.
[3] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[4] Data receive completed judgment.
[5] Read receive data.
[6] Clear IRIC flag (cancel wait state).
[7] Set acknowledge data for final receive.
[8] Wait time until TRS setting.
[9] Set TRS to generate stop condition.
[10] Read receive data.
[11] Clear IRIC flag (cancel wait state).
[12] Receive wait state (IRIC set at falling edge of 8th clock cycle)
[13] Data receive completed judgment.
[14] Clear IRIC flag (cancel wait state).
[15] Cancel wait mode
[16] Read final receive data.
[17] Generate stop condition.
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
or
Wait for end of reception of 1 byte (IRIC set at rising edge
of 9th clock cycle).
Clear IRIC flag. (IRIC flag should be cleared when WAIT = 0.)