HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 688

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI)
15.10.5 Restrictions on Use of DMAC* or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
• When RDR is read by the DMAC* or the DTC, be sure to set the activation source to the
• The flag is cleared only when DISEL in DTC is 0 with the transfer counter not being 0. When
Note: * Supported only by the H8S/2239 Group.
Note: * Supported only by the H8S/2239 Group.
15.10.6 Operation in Case of Mode Transition
• Transmission
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REJ09B0054-0600
input until at least 5 φ clock cycles after the TDR is updated by the DMAC* or the DTC.
Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated
(figure 15.38).
relevant SCI reception data full interrupt (RXI).
DISEL is 1, or DISEL is 0 with the transfer counter being 0, the flag should be cleared by
CPU. Note that transmitting, in particular, may not successfully be executed unless the TDRE
flag is cleared by CPU.
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition.
TSR, TDR, and SSR are reset. The output pin states in module stop mode, software standby
mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and
becomes high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined. When transmitting without
changing the transmit mode after the relevant mode is cleared, transmission can be started by
setting TE to 1 again, and performing the following sequence: SSR read → TDR write →
Figure 15.38 Example of Clocked Synchronous Transmission by DMAC* or DTC
SCK
TDRE
Serial data
Note: When operating on an external clock, set t > 4 clocks.
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7