HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 735

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

16.4.8
The I
the slave address and the R/W bit, confirmation of reception with acknowledge bit, indication of
the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out in
conjunction CPU processing by means of interrupts.
Table 16.5 shows some example of processing using the DTC. These examples assume that the
number of transfer data bytes is know in slave mode.
Table 16.5 Flags and Transfer States
Item
Slave address +
R/W bit
Transmission/
reception
Dummy data
read
Actual data
transmission/rece
ption
Dummy data
(H'FF) write
Last frame
processing
Transfer request
processing after
last frame
processing
Setting of
number of DTC
transfer data
frames
2
C bus format provides for selection of the slave device and transfer direction by means of
Operation Using the DTC
Master Transmit
Mode
Transmission by
DTC (ICDR write)
⎯
Transmission by
DTC (ICDR write)
⎯
Not necessary
1st time: Clearing
by CPU
2nd time: End
condition issuance
by CPU
Transmission:
Actual data count +
1 (+ 1 equivalent to
slave address +
R/W bits)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by
DTC (ICDR read)
⎯
Reception by
CPU (ICDR read)
Not necessary
Reception: Actual
data count
Section 16 I
Rev. 6.00 Mar. 18, 2010 Page 673 of 982
Slave Transmit
Mode
Reception by CPU
(ICDR read)
⎯
Transmission by
DTC (ICDR write)
Processing by DTC
(ICDR write)
Not necessary
Automatic clearing
on detection of end
condition during
transmission of
dummy data (H'FF)
Transmission:
Actual data count + 1
(+ 1 equivalent to
dummy data (H'FF))
2
C Bus Interface (IIC) (Option)
Slave Receive
Mode
Reception by CPU
(ICDR read)
⎯
Reception by DTC
(ICDR read)
⎯
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count
REJ09B0054-0600