HD64F2239TF20I Renesas Electronics America, HD64F2239TF20I Datasheet - Page 453

• Manufacturer Part Number: HD64F2239TF20I
• Description: MCU 3V 384K I-TEMP 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2200r

Specifications of HD64F2239TF20I

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 72
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

11.3.4
The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU
of the H8S/2227 Group has a total of three TIER registers, one each for channels 0 to 2. In other
groups, the TPU has a total of six TIER registers, one each for channels 0 to 5.
Bit
7
6
5
4
3
Bit Name
TTGE
—
TCIEU
TCIEV
TGIED
Timer Interrupt Enable Register (TIER)
Initial value
0
1
0
0
0
R/W
R/W
—
R/W
R/W
R/W
Description
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
Reserved
This bit is always read as 1 and cannot be
modified.
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by
the TCFU flag when the TCFU flag in TSR is set to
1 in channels 1, 2, 4 * , and 5 * .
In channels 0 and 3 * , bit 5 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by
the TCFV flag when the TCFV flag in TSR is set to
1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by
the TGFD bit when the TGFD bit in TSR is set to 1
in channels 0 and 3 * .
In channels 1, 2, 4 * , and 5 * , bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
Rev. 6.00 Mar. 18, 2010 Page 391 of 982
Section 11 16-Bit Timer Pulse Unit (TPU)
REJ09B0054-0600