CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 101

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

ATA-5 Controller
5.4.2.5
The ATAC supports UDMA/66. It utilizes the standard IDE
bus master functionality to interface, initiate, and control
the transfer. The UDMA/66 definition also incorporates a
Cyclic Redundancy Checking (CRC) error checking proto-
col to detect errors.
The UDMA/66 protocol requires no extra signal pins on the
IDE connector. The ATAC redefines three standard IDE
control signals when in UDMA/66 mode. These definitions
are shown in Table 5-9.
All other signals on the IDE connector retain their func-
tional definitions during the UDMA/66 operation.
IDE_IOW# is defined as STOP for both read and write
transfers to request to stop a transaction.
IDE_IOR# is redefined as DMARDY# for transferring data
from the IDE device to the ATAC. It is used by the ATAC to
signal when it is ready to transfer data and to add wait
states to the current transaction. The IDE_IOR# signal is
defined as STROBE for transferring data from the ATAC to
the IDE device. It is the data strobe signal driven by the
ATAC on which data is transferred during each rising and
falling edge transition.
IDE_IORDY is redefined as STROBE for transferring data
from the IDE device to the ATAC during a read cycle. It is
the data strobe signal driven by the IDE device on which
data is transferred during each rising and falling edge tran-
sition. IDE_IORDY is defined as DMARDY# during a write
cycle for transferring data from the ATAC to the IDE
device. It is used by the IDE device to signal when it is
ready to transfer data and to add wait states to the current
transaction.
UDMA/66 data transfer consists of three phases: a startup
phase, a data transfer phase, and a burst termination
phase.
The IDE device begins the startup phase by asserting
IDE_DREQ. When ready to begin the transfer, the ATAC
asserts IDE_DACK#. When IDE_DACK# is asserted, the
ATAC drives IDE_CS0# and IDE_CS1# asserted, and
IDE_ADDR[2:0] low. For write cycles, the ATAC negates
STOP, waits for the IDE device to assert DMARDY#, and
then drives the first data word and STROBE signal. For
read cycles, the ATAC negates STOP and asserts
DMARDY#. The IDE device then sends the first data word
and asserts STROBE.
AMD Geode™ CS5535 Companion Device Data Book
IDE Channel
IDE_IORDY
IDE_IOW#
IDE_IOR#
Signal
Table 5-9. UDMA/66 Signal Definitions
UDMA/66 Mode
Read Cycle
DMARDY#
UDMA/66
STROBE
STOP
Write Cycle
DMARDY#
UDMA/66
STROBE
STOP
The data transfer phase continues the burst transfers with
the ATAC and the IDE via providing data, toggling
STROBE and DMARDY#. IDE_DATA[15:0] is latched by
the receiver on each rising and falling edge of STROBE.
The transmitter can pause the burst cycle by holding
STROBE high or low, and resume the burst cycle by again
toggling STROBE. The receiver can pause the burst cycle
by negating DMARDY# and resumes the burst cycle by
asserting DMARDY#.
The current burst cycle can be terminated by either the
transmitter or receiver. A burst cycle must first be paused,
as described above, before it can be terminated. The
ATAC can then stop the burst cycle by asserting STOP,
with
IDE_DREQ. The transmitter then drives the STROBE sig-
nal to a high level. The ATAC then puts the result of the
CRC calculation onto IDE_DATA[15:0] while de-asserting
IDE_DACK#. The IDE device latches the CRC value on the
rising edge of IDE_DACK#.
The CRC value is used for error checking on UDMA/66
transfers. The CRC value is calculated for all data by both
the ATAC and the IDE device during the UDMA/66 burst
transfer cycles. This result of the CRC calculation is
defined as all data transferred with a valid STROBE edge
while IDE_DACK# is asserted. At the end of the burst
transfer, the ATAC drives the result of the CRC calculation
onto IDE_DATA[15:0], which is then strobed by the de-
assertion of IDE_DACK#. The IDE device compares the
CRC result of the ATAC to its own and reports an error if
there is a mismatch.
The timings for UDMA/66 are programmed into the DMA
control registers:
• Channel 0 Drive 0 DMA (ATAC_CH0D0_DMA) (MSR
• Channel 0 Drive 1 DMA (ATAC_CH0D1_DMA) (MSR
The bit formats for these registers are given in Section
6.4.3 "ATAC Native Registers" on page 274. Note that
MSR 51300021h[20] is used to select either MDMA or
UDMA mode. Bit 20 = 0 selects MDMA mode. If bit 20 = 1,
then UDMA/66 mode is selected. Once mode selection is
made using this bit, the remaining DMA registers also
operate in the selected mode.
Also listed in the bit formats are recommended values for
both MDMA modes 0-2 and UDMA/66 modes 0-4. Note
that these values are only recommended settings and are
not 100% tested.
51300021h)
51300023h)
the
IDE
device
31506B
acknowledging
by
negating
101