CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 398

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.12.4
The bit formats of the registers in Bank 1 are summarized in Table 6-36. Detailed descriptions of each register follow.
6.12.4.1 Legacy Baud Generator Divisor Port
Legacy Baud Generator Divisor Low Byte (LBGD_L)
I/O Offset
Type
Reset Value
The Legacy Baud Generator Divisor (LBGD) port provides an alternate data path to the Baud Divisor Generator register.
LBGD is a 16-bit wide port split into two bytes, LBGD_L an LBGD_H, occupying consecutive address locations. This port is
implemented to maintain compatibility with 16550 standard and to support existing legacy software packages. New soft-
ware should use the BGD port in Bank 2 to access the baud generator divisor register.
The programmable baud rates in the non-extended mode are achieved by dividing a 24 MHz clock by a prescale value of
13, 1.625 or 1. This prescale value is selected by the PRESL field of EXCR2 (Section 6.12.5.4 on page 403).
Divisor values between 1 and 2
page 399). The baud generator divisor must be loaded during initialization to ensure proper operation of the baud genera-
tor. Upon loading either part of it, the baud generator counter is immediately loaded. Table 6-38 shows typical baud divi-
sors. After reset, the divisor register contents are indeterminate.
If the UART is in extended mode, any access to the LBGD_L or LBGD_H causes a reset to the default non-extended mode
(i.e., 16550 mode). To access a baud generator divisor when in extended mode, use the port pair in Bank 2 (see Section
6.12.5.1 "Baud Generator Divisor Port" on page 400).
Table 6-37 shows the bits that are cleared when fallback occurs during extended or non-extended modes. If the UART is in
non-extended mode and the LOCK bit is 1, the content of the divisor (BGD) port is not be effected and no other action is
taken.
398
04-07h
Offset
Register
00h
01h
02h
03h
EXCR1
EXCR2
I/O
IRCR1
Name
MCR
Register
Bank 1 Register Descriptions
Name
LBGD_L
LBGD_H
RSVD
LCR
BSR
RSVD
Extended Mode LOCK = x
00h
R/W
xxh
31506B
0, 5 and 7
2 and 3
2 to 7
0 to 5
BKSE
BKSE
16
7
-1 can be used (0 cannot be used, see Table 6-38 "Baud Generator Divisor Settings" on
Table 6-37. Bits Cleared on Fallback
SBRK
6
Table 6-36. Bank 1 Bit Map
UART Mode and LOCK Bit before Fallback
Non-Extended Mode LOCK = 0
STKP
5
5 and 7
Legacy Baud Generator Divisor High Byte (LBGD_H)
I/O Offset
Type
Reset Value
0 to 5
None
None
EPS
4
LBGD[15:8]
LBGD[7:0]
RSVD
RSVD
AMD Geode™ CS5535 Companion Device Data Book
Bits
BSR[6:0]
PEN
3
01h
R/W
xxh
UART and IR Port Register Descriptions
Non-Extended Mode LOCK = 1
STB
2
None
None
None
None
WLS1
1
WLS0
0