CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 492

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.17.2.4 MFGPT[x] Setup (MFGPT[x]_SETUP)
MFGPT0 to MFGPT5 Setup registers are in the Working power domain while MFGPT6 and MFGPT7 Setup registers are in
the Standby power domain. Bits [11:0] are write-once; bit 12 is read-only.
MFGPT0 Setup (MFGPT0_SETUP)
MFGPT I/O Offset
Type
Reset Value
MFGPT1 Setup (MFGPT1_SETUP)
MFGPT I/O Offset
Type
Reset Value
MFGPT2 Setup (MFGPT2_SETUP)
MFGPT I/O Offset
Type
Reset Value
MFGPT3 Setup (MFGPT3_SETUP)
MFGPT I/O Offset
Type
Reset Value
492
15
Bit
15
14
13
12
11
14
Name
MFGPT_CNT_EN
MFGPT_CMP2
MFGPT_CMP1
MFGPT_SETUP (RO)
MFGPT_STOP_EN
13
06h
16h
R/W
0000h
0Eh
R/W
0000h
R/W
0000h
1Eh
R/W
0000h
31506B
12
11
Description
Counter Enable. Enable MFGPT for counting. 0: Disable; 1: Enable.
Compare 2 Output Status. If Conditioning Mode is set to Event, writing this bit to
a 1 clears the event until the next time Compare 2 goes from low-to-high; reading
returns the event status. For other modes, this bit follows current compare output
values and writes to this bit have no effect. When Compare 2 value is met, the
counter is reset and counting continues.
Compare 1 Output Status. If Conditioning Mode is set to Event, writing this bit to
a 1 clears the event until the next time Compare 1 goes from low-to-high; reading
returns the event status. For other modes, this bit follows current compare output
values and writes to this bit have no effect. When Compare 2 value is met, count-
ing stops. Counter is reset and restarted only by external enable or dis-
abling/enabling.
Setup (Read Only). Any value written to this bit is a ‘don’t care’. From reset, this
bit is low. If low, it indicates the MFGPT has not been setup and is currently dis-
abled. On the first write to this register, bits [11:0] are established per the write
and this bit is set to a 1. After this bit is set on the first write, bits [12:0] cannot be
changed and subsequent writes are ‘don’t care’.
Stop Enable (Write Once). Enable counter to Stop on Sleep state for MFGPT0
to MFGPT5, or Standby state for MFGPT6 and MFGPT7. 0: Disable; 1: Enable.
MFGPT[x]_SETUP Bit Descriptions
10
MFGPT[x]_SETUP Register Map
MFGPT_CMP2
9
MODE
8
MFGPT_CMP1
MFGPT4 Setup (MFGPT4_SETUP)
MFGPT I/O Offset
Type
Reset Value
MFGPT5 Setup (MFGPT5_SETUP)
MFGPT I/O Offset
Type
Reset Value
MFGPT6 Setup (MFGPT6_SETUP)
MFGPT I/O Offset
Type
Reset Value
MFGPT7 Setup (MFGPT7_SETUP)
MFGPT I/O Offset
Type
Reset Value
Multi-Function General Purpose Timer Register Descriptions
7
MODE
AMD Geode™ CS5535 Companion Device Data Book
6
5
26h
R/W
0000h
2Eh
R/W
0000h
36h
R/W
0000h
3Eh
R/W
0000h
4
3
MFGPT_SCALE
2
1
0