CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 64

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

4.5.2
Each of the clock domains listed in Table 4-3 on page 63 is
subject to various GLCP controls and status registers
except those with “Note 3”. These registers and a brief
description of each is provided:
• GLCP Clock Active (GLCP_CLKACTIVE), MSR
• GLCP Clock Control (GLCP_CLKOFF), MSR
• GLCP Clock Mask for Debug Clock Stop Action
• GLCP Clock Active Mask for Suspend Acknowledge
• GLCP Clock Mask for Sleep Request
All of the registers above have the same layout, where
each bit is associated with a clock domain. The layout and
recommended operating values for the registers is pro-
vided in Table 6-73 "Clock Mapping / Operational Settings"
on page 536.
64
51700011h: A 1 indicates the corresponding clock is
active. This is a read only register.
51700010h: A 1 indicates the corresponding clock is to
be disabled immediately and unconditionally. Not
normally used operationally. Debug only.
(GLCP_CLKDISABLE), MSR 51700012h: A 1 indicates
the corresponding clock is to be disabled by debug logic
via a debug event or trigger. Not normally used opera-
tionally. Debug only.
(GLCP_CLK4ACK), MSR 51700013h: A 1 indicates the
corresponding clock is to be monitored during a power
management Sleep operation. When all the clocks with
associated 1s go inactive, the GLCP sends a Sleep
Acknowledge to the Power Management Controller.
This register is used during Sleep sequences and
requires the CLK_DLY_EN bit in GLCP_GLB_PM (MSR
5170000Bh[1]) to be 0.
(GLCP_PMCLKDISABLE), MSR 51700009h: A 1 indi-
cates the corresponding clock is to be disabled uncondi-
tionally during a power management Sleep operation.
Clocks are disabled when the GLCP completes all of its
Sleep Request operations and sends a Sleep Acknowl-
edge to the Power Management Controller.
Clock Controls and Setup
31506B
4.5.2.1
• GLCP Debug Clock Control (GLCP_DBGCLKCTL),
• GLCP Global Power Management Control
• GLCP Clock Disable Delay Value
MSR 51700016h: Set all bits to 0. This turns off all
clocks to debug features; not needed during normal
operation.
(GLCP_GLB_PM), MSR 5170000Bh: Set all bits to 0.
This disables the use of the fixed delay in
GLCP_CLK_DIS_DELAY and enables the use of
GLCP_CLK4ACK.
(GLCP_CLK_DIS_DELAY), MSR 51700008h: Set all
bits to 0. Since use of this register is disabled by setting
all GLCP_DBGCLKCTL bits to 0, the actual value of this
register is a “don’t care”; it is set here for completeness.
If use of GLCP_CLK_DIS_DELAY is desired, set the
CLK_DLY_EN bit in GLCP_GLB_PM (MSR
5170000Bh[1] = 1). This will disable the use of
GLCP_CLK4ACK and shut off the clocks in
GLCP_PMCLKDISABLE after the
GLCP_CLK_DIS_DELAY expires. This delay is
measured in PCI clock edges.
AMD Geode™ CS5535 Companion Device Data Book
Additional Setup Operations
Global Concepts and Features