CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 164

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

5.15.5.2 Input Event Counter Conditioning Function
The event counter is one half of a filter/event conditioning
circuit, and is in series with its associated filter. (The other
half is the digital filter.) It counts events and can produce
an output when a predefined count is reached. The event
counter may be down-counted by writing to a particular
address. It may be used as a rate counter that may be peri-
odically read, and that produces no output at all.
To use one of the eight event counters, it must first be
assigned to one of the GPIO inputs using one of the
GPIO_FE[x]_SEL registers (where X is the number of the
Filter/Event pair, 0 to 7). Then the associated digital filter
must be enabled, through either the GPIOL_IN_FLTR_EN
or GPIOH_IN_FLTR_EN registers, depending on whether
the selected GPIO is in the high [28:16] or low [15:0] bank.
If digital filtering is not required, program the associated
GPIO_FLTR[x]_AMNT registers to 0000h. Finally, the
desired
_COMPARE) must be determined and then programmed
to establish the number of events that will produce an out-
put when that count has been reached.
The event counter is based upon a 16-bit programmable
up/down counter. The up-down counter counts positive
edges of the selected GPIO input and produces a constant
or level output when the GPIO_EVNTCNT[x] (counter
value) exceeds the CPIO_EVNTCNT[x]_COMPARE (com-
pare value). The output can be read as the GPIO and/or
used to drive an auxiliary input.
The counter may be counted down one count by writing to
one of two addresses, depending on which bank (High or
Low) the associated GPIO resides in. Knowledge of which
GPIO is associated with the event counter is required,
since these two decrementer registers have a dedicated bit
for each GPIO. When counted down, this counter, unlike
the counter in the digital filter, will roll over from 0000h to
FFFFh. Typically, decrementing is used to clear an inter-
rupt or power management event as part of the associated
service routine.
5.15.5.3 Uses of the Event Counter
Such an auxiliary input could be used to drive an ASMI or
maskable interrupt. Assume the compare value is set to 0.
The service routine clears the ASMI by decrementing the
counter via the mechanism illustrated. If additional events
have occurred, the count does not decrement to 0 and the
ASMI remains asserted. The count up and down inputs are
synchronized such that false values are not created if up
and down pulses occur at or near the same instant in time.
The counter will not decrement through 0.
Alternatively, the compare value could be set to a higher
value to trigger an ASMI or interrupt when a certain number
of events has occurred. In this case, the ASMI or interrupt
is cleared by writing the counter to 0.
Lastly, the input value may be ignored and the event
counter used as a rate indicator. If software reads the
counter at a fixed periodic interval, an input pulse rate may
be measured. Such an approach may be used to imple-
164
“compare
31506B
value”
(GPIO_EVNTCNT[x]
ment a tachometer function. The counter will increment
past all Fs back to 0.
As suggested above, the counter may be read or written
under software control. The read and write operations are
synchronized such that false values are not created if
count up pulses occur at or near the same instant in time.
5.15.5.4 Input Edge Conditioning Function
The Edge Detection function is illustrated as part of Figure
5-49 on page 162. It is normally used to generate an ASMI
or maskable interrupt on each positive and/or negative
edge of an input signal. Use of this function simultaneously
with the event counter function is somewhat logically mutu-
ally exclusive, but is not prevented in hardware.
Each GPIO has the optional edge detection function.
The reset default for the detection circuit establishes a 0
level
GPIO[x]_NEGEDGE_EN. When both are set to 0, the edge
detection function is disabled. If either a positive or nega-
tive edge detection is enabled, an active high output is pro-
duced when the appropriate edge occurs. This level must
be
GPIO[x]_POSEDGE_STS or the GPIO[x]NEGEDGE_STS
registers, whichever is appropriate. If another edge occurs
before clearing, the active high output is not affected. If the
clear action occurs at the “same time” as another edge, the
result is not defined.
Each edge detection function is controlled by four registers
as follows:
• Positive Edge Enable (GPIO[x]_POSEDGE_EN).
• Negative Edge Enable (GPIO[x]_NEGEDGE_EN).
• Positive Edge Status (GPIO[x]_POSEDGE_STS). Set
• Negative Edge Status (GPIO[x]_POSEDGE_STS). Set
Enabled if feature bit is high.
Enabled if feature bit is high.
indicates edge. Write 1 to clear.
indicates edge. Write 1 to clear.
cleared
AMD Geode™ CS5535 Companion Device Data Book
on
by
GPIO[x]_POSEDGE_EN
writing
General Purpose Input/Output
to
either
and
the