CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 44

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.2.5
3.2.6
44
Signal Name
SMB_CLK
SMB_DATA
Signal Name
(Note 1)
LPC_CLK
LPC_AD[3:0]
LPC_DRQ#
System Management Bus (SMB) Interface
Low Pin Count (LPC) Interface
31506B
K1, J1, J2,
Ball No.
Ball No.
G3
G1
H1
H2
F1
Type
Type
I/O
I/O
I/O
I
I
Description
SMB Clock. This is the clock for the System Management bus. It is ini-
tiated by the master of the current transaction. Data is sampled during
the high state of the clock.
An external pull-up resistor is required.
Shared with GPIO14. Set GPIO14 to IN_AUX1 and OUT_AUX1 modes
simultaneously to use as SMB_CLK. See Table 3-8 "GPIO Options" on
page 47.
External voltage applied to this ball should not exceed V
SMB Data. This is the bidirectional data line for the System Manage-
ment bus. Data may change during the low state of the SMB clock and
should remain stable during the high state.
An external pull-up resistor is required.
Shared with GPIO15. Set GPIO15 to IN_AUX1 and OUT_AUX1 modes
simultaneously to use as SMB_DATA. See Table 3-8 "GPIO Options"
on page 47.
External voltage applied to this ball should not exceed V
Description
LPC Clock. 33 MHz LPC bus shift clock.
LPC Address/Data Bus. This is the 4-bit LPC bus. Address, control,
and data are transferred on this bus between the Geode CS5535 com-
panion device and LPC devices.
An external pull-up of 100 kΩ is required on these balls (if used in LPC
mode) to maintain a high level when the signals are in TRI-STATE
mode. From reset, these signals are not driven.
LPC_AD3 is shared with GPIO19.
LPC_AD2 is shared with GPIO18.
LPC_AD1 is shared with GPIO17.
LPC_AD0 is shared with GPIO16.
See Table 3-8 "GPIO Options" on page 47 for further details.
LPC DMA Request. This is the LPC DMA request signal. Peripherals
requiring service pull it low and then place a serially-encoded
requested channel number on this line to initiate a DMA transfer.
If the device wakes up from Sleep, at least six LPC_CLKs must occur
before this input is asserted.
Shared with GPIO20. See Table 3-8 "GPIO Options" on page 47. Tie
high if selected as LPC_DRQ# but not used.
AMD Geode™ CS5535 Companion Device Data Book
Signal Definitions
IO
IO
.
.