CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 504

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.18.3
The registers listed in this sub-section are not ACPI registers, but are used to support power management implementation.
6.18.3.1 PM Sleep Start Delay (PM_SSD)
PMS I/O Offset
Type
Reset Value
504
15
11:0
Bit
Bit
15
14
13
12
4
3
2
1
0
RSVD
PM Support Registers
14
Name
UART2_PME_EN
UART1_PME_EN
SMB_PME_EN
PIC_ASMI_PME_
EN
PIC_IRQ_PME_
EN
Name
SLP_EN_INDIC
RSVD
SLP_WRT_EN
SLP_DELAY_EN
SLP_DELAY
13
00h
R/W
0000h
31506B
12
11
Description
UART #2 PME Enable. When set high, this bit enables the generation of a PME to the
system if a PME occurs via UART #2. Write this bit low to disable the generation of a
PME from this source.
UART #1 PME Enable. When set high, this bit enables the generation of a PME to the
system if a PME occurs via UART #2. Write this bit low to disable the generation of a
PME from this source.
SMB PME Enable. When set high, this bit enables the generation of a PME to the sys-
tem if a PME occurs via the SMB. Write this bit low to disable the generation of a PME
from this source.
PIC ASMI PME Enable. When set high, this bit enables the generation of a PME to the
system if a PME occurs due to a PIC ASMI. Write this bit low to disable the generation
of a PME from this source.
PIC Interrupt PME Enable. When set high, this bit enables the generation of a PME to
the system if a PME occurs due to a PIC Interrupt. Write this bit low to disable the gen-
eration of a PME from this source
Description
Sleep Enable Indicator. If SLP_EN (ACPI I/O Offset 08h[13]) was written to a 1, then
this bit reads high. If this bit is written to a 1, the Sleep sequence is aborted. Writing a 0
to this bit has no effect. This bit always clears on a Sleep or Standby wakeup.
Reserved. By convention write 0. Reads return value written.
Sleep Write Enable. Must be high in order to change bits 12 and [11:0]
(SLP_DELAY_EN and SLP_DELAY). Reads of this bit always return 0.
Sleep Delay Enable. Must be high to enable the delay specified in bits [11:0]
(SLP_DELAY). Reads return value written.
Sleep Delay. Indicates the number of 3.57954 MHz clock edges to wait before begin-
ning the Sleep or Standby process as defined by SLP_EN (ACPI I/O Offset 08h[13]).
Bit 12 (SLP_DELAY_EN) must be high to enable this delay. Reads return the value writ-
ten.
PM_GPE0_EN Bit Descriptions (Continued)
10
PM_SSD Bit Descriptions
PM_SSD Register Map
9
8
7
SLP_DELAY
AMD Geode™ CS5535 Companion Device Data Book
Power Management Controller Register Descriptions
6
5
4
3
2
1
0