CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 394

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
MCR, Non-Extended Mode (EXCR1.EXT_SL = 0)
6.12.3.6 Link Status Register (LSR)
I/O Offset
Type
Reset Value
LSR provides status information concerning data transfer. Upon reset, this register assumes the value of 60h. The bit defi-
nitions change depending upon the operation mode of the functional block.
Bits 1 to 4 of the LSR indicate link status events. These bits are sticky (accumulate any conditions occurred since the last
time the register was read). They are cleared when one of the following events occur:
• Hardware reset
• Receiver soft reset (via the FIFO Control register)
• LSR register read
The LSR is intended for read operations only. Writing to the LSR is not permitted.
394
Bit
7:5
4
3
2
1
0
ER_INF
7
7
Name
RSVD
LOOP
ISEN or
DCDLP
RILP
RTS
DTR
TXEMP
05h
RO
60h
RSVD
6
6
31506B
Description
Reserved. Must written as 0.
Loopback Enable. This bit accesses the same internal register as LOOP (bit 4) of the
EXCR1 register. (See Section 6.12.5.2 on page 400 for more information on Loopback
mode).
0: Loopback disabled. (Default.)
1: Loopback enabled.
Interrupt Signal Enable or DCD Loopback. In normal operation (standard 16450 or 16550)
mode, this bit controls the interrupt signal and must be set to 1 in order to enable the inter-
rupt request signal. In loopback mode, this bit internally drives DCD, and the interrupt signal
is always enabled.
Ring Indicator in Loopback. When loopback is enabled, this bit internally drives RI. Other-
wise, it is unused.
Request To Send. When loopback is enabled, this bit drives CTS internally. Otherwise, it is
unused.
Data Terminal Ready. When loopback is enabled, this bit internally drives DSR. Otherwise,
it is unused.
TXRDY
MCR Non-Extended Mode Bit Descriptions
MCR Non-Extended Mode Register Map
5
5
LSR Register Map
LOOP
BRK
4
4
ISEN or DCDLP
FE
3
3
AMD Geode™ CS5535 Companion Device Data Book
RILP
PE
2
2
UART and IR Port Register Descriptions
RTS
OE
1
1
RXDA
DTR
0
0

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