CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 129

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

System Management Bus Controller
5.11.1
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (SCL).
Consequently, throughout the clock’s high period, the data
should remain stable (see Figure 5-24). Any changes on
the SDA line during the high state of SCL and in the middle
of a transaction aborts the current transaction. New data
should be sent during the low SCL state. This protocol per-
mits a single data line to transfer both command/control
information and data, using the synchronous serial clock.
Each data transaction is composed of a START condition,
a number of byte transfers (set by the software), and a
STOP condition to terminate the transaction. Each byte is
transferred with the most significant bit first, and after each
byte (8 bits), an Acknowledge signal must follow. The fol-
lowing subsections provide further details of this process.
During each clock cycle, the slave can stall the master
while it handles the previous data or prepares new data.
This can be done for each bit transferred, or on a byte
boundary, by the slave holding SCL low to extend the
clock-low period. Typically, slaves extend the first clock
cycle of a transfer if a byte read has not yet been stored, or
if the next byte to be transmitted is not yet ready. Some
microcontrollers, with limited hardware support for SMB,
extend the SMB after each bit, thus allowing the software
to handle this bit.
AMD Geode™ CS5535 Companion Device Data Book
SDA
SCL
Data Transactions
Figure 5-24. SMB Bit Transfer
Data Line
Stable:
Data Valid
Change
of Data
Allowed
5.11.1.1 START and STOP Conditions
The SMB master generates START and STOP conditions
(control codes). After a START condition is generated, the
bus is considered busy and retains this status for a certain
time after a STOP condition is generated. A high-to-low
transition of the data line (SDA) while the clock (SCL) is
high indicates a START condition. A low-to-high transition
of the SDA line while the SCL is high indicates a STOP
condition (see Figure 5-25).
In addition to the first START condition, a repeated START
condition can be generated in the middle of a transaction.
This allows another device to arbitrate the
in the direction of data transfer.
Figure 5-25. SMB START and STOP Conditions
SDA
SCL
START
Condition
S
31506B
bus,
STOP
Condition
or a change
P
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