CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 88

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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5.2.15
This section describes how various errors are handled by
the PCI Bus Interface block.
Since PERR# is not implemented on the Geode CS5535
companion device or the Geode GX processor, error
reporting via this signal is not supported. In a Geode GX
processor/CS5535 companion device system, other PCI
devices that do have the PERR# pin must have a pull-up.
5.2.16
When performing an out-bound write on PCI, three errors
may occur: master abort, target abort, and parity error.
When a master or target abort occurs, the PCI Bus Inter-
face block will flush any stored write data. If enabled, an
ASMI is generated. ASMI generation is enabled and
reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h).
Parity errors are detected and handled by the processor.
The failed transaction will not be retried.
5.2.17
When performing an out-bound read on PCI, three errors
may occur: master abort, target abort, and detected parity
error. When a master or target abort occurs, the PCI Bus
Interface block will return the expected amount of data. If
enabled, an ASMI is generated. ASMI generation is
enabled and reported in GLPCI_SB GLD_MSR_SMI (MSR
51000002h). Parity errors are detected and handled by the
processor. The failed transaction will not be retried.
88
Exception Handling
Out-Bound Write Exceptions
Out-Bound Read Exceptions
31506B
5.2.18
When performing an in-bound write from PCI, two errors
may occur: a detected parity error and a GLIU exception. A
GLIU exception cannot be relayed back to the originating
PCI bus master, because in-bound PCI writes are always
posted. When a parity error is detected, an ASMI is gener-
ated if it is enabled. ASMI generation is enabled and
reported in GLPCI_SB GLD_MSR_SMI (MSR 51000002h).
However, the corrupted write data will be passed along to
the GLIU.
5.2.19
When performing an in-bound read from the GLIU, the
EXCEP flag may be set on any received bus-WORD of
data. This may be due to an address configuration error
caused by software or by an error reported by the source of
data. The asynchronous ERR and/or SMI bit will be set by
the PCI Bus Interface block and the read data, valid or not,
will be passed to the PCI Bus Interface block along with the
associated exceptions. The PCI Bus Interface block should
simply pass the read response data along to the PCI bus.
AMD Geode™ CS5535 Companion Device Data Book
In-Bound Write Exceptions
In-Bound Read Exceptions
GeodeLink™ PCI South Bridge

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