CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 34

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

3.1.2
Two balls on the device, L2 and L3, the Boot Options
Select balls (BOS[1:0]), serve to specify the location of the
boot device as the system undergoes a full reset. Since
boot devices may reside in Flash or on an IDE device, the
IDE/Flash interface is necessarily selected as operating in
one of the two modes by the Boot Options. After Reset, the
function of these interfaces may be changed with the Ball
Options MSR (see Section 3.1.3 "Ball Options"). Both
these balls are multiplexed with other functions (as identi-
fied in Section 3.2.7 "Audio Codec 97 Interface" on page
45) and function as BOS[1:0] only when RESET_OUT# is
asserted. Table 3-5 indicates how these two balls should
be configured to select the desired boot device. Both balls
contain an internal pull-up, active only during reset, so if a
34
31:12
11:10
(Ball L2)
Bit
9:8
BOS1
7
0
0
1
1
Boot Options
Name
RSVD
SEC_BOOT_LOC
BOOT_OP_
LATCHED (RO)
RSVD
(Ball L3)
BOS0
0
1
0
1
31506B
Description
Boot from Memory Device on the LPC Bus. IDE pins come up connected to IDE Control-
ler (see Section 3.2.3 "IDE/Flash Interface Signals" on page 40 and Table 3-6
"DIVIL_BALL_OPT (MSR 51400015h)").
Reserved.
Boot from NOR Flash on the IDE Bus. IDE pins come up connected to Flash Controller
(see Section 3.2.3 "IDE/Flash Interface Signals" on page 40 and Table 3-6
"DIVIL_BALL_OPT (MSR 51400015h)").
NOR Flash, ROM, or other random access devices must be connected to “FLASH_CS_3”.
Boot from Firmware Hub on the LPC Bus. IDE pins come up connected to IDE Control-
ler (see Section 3.2.3 "IDE/Flash Interface Signals" on page 40 and Table 3-6
"DIVIL_BALL_OPT (MSR 51400015h)").
Table 3-6. DIVIL_BALL_OPT (MSR 51400015h)
Description
Reserved. Reads always return 0. Writes have no effect; by convention, always write 0.
Secondary Boot Location. Determines which chip select asserts for addresses in the
range F00F0000h to F00F3FFFh. Defaults to the same value as boot option:
00: LPC ROM.
01: Reserved .
10: Flash.
11: FirmWare Hub.
Latched Value of Boot Option (Read Only). For values, see Table 3-5 "Boot Options
Selection".
Reserved. Reads return value written. By convention, always write 0. Defaults low.
Table 3-5. Boot Options Selection
ball is required to be high during this time, it may be left
unconnected. If a ball is desired to be low during reset, a
pull-down (i.e., not a hard tie to ground) should be added.
During reset, both balls’ output drivers are in the TRI-
STATE mode.
3.1.3
Table 3-6 shows the Ball Options MSR (DIVIL MSR
51400015h), through which the function of certain groups
of multiplexed balls may be dynamically changed after the
reset period ends. Specifically, the functions LPC/GPIO
and IDE/Flash groups are selected, and certain individual
balls, as specified in the MSR, are controlled.
AMD Geode™ CS5535 Companion Device Data Book
Ball Options
Signal Definitions