CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 343

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Programmable Interval Timer Register Descriptions
6.8.2
6.8.2.1
I/O Address
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
Note: PIT_CNTR2_EN (PIT Counter 2 Enable) bit is located at I/O Address 61h[0] (see Section 6.8.2.8 "Port B Control
Bit
3:2
Bit
7:0
4
1
0
7
(PIT_PORTBCTL)" on page 348).
PIT Native Registers
PIT Timer 0 Counter - System (PIT_TMR0_CNTR_SYS)
Name
PIT_CNTR_ACC_
DLY_EN
RSVD
PIT_CNTR1_EN
PIT_CNTR0_EN
Name
CNTR0
40h
W
00h
6
Description
PIT Counter Access Delay Enable. Used as an access delay enable for the read and
write operations of the PIT counters. This bit introduces a 1 µs delay between succes-
sive reads and/or writes of the PIT counters. This bit is intended to ensure that older,
DOS-based programs that rely on the PIT timing access to be 1 µs still function prop-
erly.
0: Disable access delay.
1: Enable access delay.
Reserved. Read zero. Write “don’t care”.
PIT Counter 1 Enable.
0: Sets GATE1 input low.
1: Sets GATE1 input high.
PIT Counter 0 Enable.
0: Sets GATE0 input low.
1: Sets GATE0 input high.
Description
Counter 0 Value. Provides the base counter value.
PIT_CNTRL Bit Descriptions (Continued)
5
PIT_TMR0_CNTR_SYS Bit Description
PIT_TMR0_CNTR_SYS_ Register Map
4
CNTR0
3
2
31506B
1
0
343