CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 385

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
6.12.3.2 Interrupt Enable Register (IER)
I/O Offset
Type
Reset Value
IER controls the enabling of various interrupts. Some interrupts are common to all operating modes of the functional block,
while others are mode-specific. Bits [7:4] can be set in extended mode only. They are cleared in non-extended mode.
When a bit is set to 1, an interrupt is generated when the corresponding event occurs. In non-extended mode, most events
can be identified by reading the LSR and MSR. The receiver high-data-level event can only be identified by reading the EIR
register after the corresponding interrupt has been generated. In extended mode, events are identified by event flags in the
EIR register.
The bitmap of the IER varies depending on the operating mode of the functional block. The modes can be divided into the
two groups and is selected via the EXT_SL bit in the EXCR1 register (Bank 2, I/O Offset 02h[0]):
• UART, Sharp-IR, SIR and CEIR in extended mode (EXT_SL = 1)
• UART, Sharp-IR and SIR in non-extended mode (EXT_SL = 0)
IER, Extended Mode: UART, SIR, Sharp-IR and CEIR (EXCR1.EXT_SL = 1)
Notes (Extended Mode Only):
1)
2)
3)
AMD Geode™ CS5535 Companion Device Data Book
Bit
7:6
If the interrupt signal drives an edge-sensitive interrupt controller input, it is advisable to disable all interrupts by clear-
ing all the IER bits upon entering the interrupt routine, and re-enable them just before exiting it. This guarantees proper
interrupt triggering in the interrupt controller should one or more interrupt events occur during execution of the interrupt
routine.
If an interrupt source must be disabled, the CPU can do so by clearing the corresponding bit of the IER register. How-
ever, if an interrupt event occurs just before the corresponding enable bit of the IER register is cleared, a spurious
interrupt may be generated. To avoid this problem, clearing of any IER bit should be done during execution of the inter-
rupt service routine. If the interrupt controller is programmed for level-sensitive interrupts, clearing IER bits can be per-
formed outside the interrupt service routine, but with the CPU interrupt disabled.
If the LSR, MSR, or EIR registers are to be polled, the interrupt sources (identified via self-clearing bits) should have
their corresponding IER bits set to 0. This prevents spurious pulses on the interrupt output pin.
5
4
3
2
1
0
7
Name
RSVD
TXEMP_IE
DMA_IE
MS_IE
LS_IE/TXHLT_IE
TXLDL_IE
RXHDL_IE
RSVD
01h
R/W
00h
6
TXEMP_IE
Description
Reserved. Write as 0.
Transmitter Empty Interrupt Enable. Setting this bit to 1 enables transmitter empty
interrupts (in all modes).
DMA Interrupt Enable. Setting this bit to 1 enables the interrupt on terminal count
when the DMA is enabled.
Modem Status Interrupt Enable. Setting this bit to 1 enables the interrupts on modem
status events.
Link Status Interrupt Enable/Transmitter Halted Interrupt Enable. Setting this bit
enables link status interrupts and transmitter halted interrupts in CEIR.
Transmitter Low-Data-Level Interrupt Enable. Setting this bit to 1 enables interrupts
when the TX_FIFO is below the threshold level or the transmitter holding register is
empty.
Receiver High-Data-Level Interrupt Enable. Setting this bit to 1 enables interrupts
when the RXD is full, or the RX_FIFO is equal to or above the RX_FIFO threshold level,
or an RX_FIFO timeout occurs.
5
IER Extended Mode Bit Descriptions
IER Extended Mode Register Map
DMA_IE
4
MS_IE
3
TXHLT_IE
LS_IE/
2
31506B
TXLDL_IE
1
RXHDL_IE
0
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