CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 512
CS5535-UDCF
Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet
1.CS5535-UDCF.pdf
(579 pages)
Specifications of CS5535-UDCF
Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Available stocks
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Part Number
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Quantity
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Part Number:
CS5535-UDCF
Manufacturer:
AMD
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6.18.3.11 PM Working Auxiliary De-assert Delay and Enable (PM_WKXD)
PMS I/O Offset
Type
Reset Value
Reads always return the value written, except for RSVD bits [29:20].
512
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
29:20
19:0
Bit
31
30
Name
RSVD
WORK_AUX_
DEASSERT_EN
RSVD
WORK_AUX_
DEASSERT_
DELAY
34h
R/W
00000000h
31506B
RSVD
Description
Reserved. By convention write 0, but may write anything.
Working Auxiliary De-assert and Delay Enable. Must be high to de-assert the
WORK_AUX output and enable its delay specified in bits [19:0]
(WORK_AUX_DEASSERT_DELAY).
Use of this control implies a system sequence into the Standby State. The PMC dis-
ables its interfaces to non-Standby portions of the component and only considers
wakeup events from Standby circuits. The PMC also immediately asserts system reset
when SLP_CLK_EN# is asserted regardless of the value of
WORK_AUX_DEASSERT_DELAY (bits [19:0]). Reset remains asserted throughout the
Standby state.
There is NOT an assert delay. The wakeup event causes the WORK_AUX output to
assert. This event is called Standby wakeup.
On wakeup, Reset continues to be applied to all non-Standby circuits for the length of
time specified in RESET_DELAY (PMS I/O Offset 38h[19:0]).
Enabling this function and/or the function in PM_WKD (PMS I/O Offset 30h[30] = 1)
causes the same Standby state events. Standby state is not entered unless
SLP_CLK_EN# is asserted.
Reserved. By convention write 0, but may write anything. Reads return 0.
WORK_AUX De-assert Delay. Indicates the number of 32 kHz clock edges to wait
from the assertion of SLP_CLK_EN# before de-asserting the WORK_AUX output. Bit
30 (WORK_AUX_DEASSERT_EN) must be high to enable this delay.
PM_WKXD Bit Descriptions
PM_WKXD Register Map
WORK_AUX_DEASSERT_DELAY
AMD Geode™ CS5535 Companion Device Data Book
Power Management Controller Register Descriptions
9
8
7
6
5
4
3
2
1
0
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