CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 183

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Flash Controller
5.18
The Geode CS5535 companion device has a Flash device
interface that supports popular NOR Flash and inexpen-
sive NAND Flash devices. This interface is shared with the
IDE interface (ATA-5 Controller (ATAC)), using the same
balls. NOR or NAND Flash may co-exist with IDE devices
using PIO (Programmed I/O) mode. The 8-bit interface
supports up to four “lanes” of byte-wide Flash devices
through use of four independent chip selects, and allows
for booting from the array. Hardware support is present for
SmartMedia-type ECC (Error Correction Code) calcula-
tions, off-loading software from having to support this task.
If Flash and IDE are both operational, an external pull-up
(10K) to IDE_DREQ0 (ball A14) is required and
IDE_DREQ0 must not be connected to the IDE device. To
switch modes, explicit software actions must occur to dis-
able one and enable the other.
Features
• Supports popular NOR Flash and inexpensive NAND
• NOR Flash and NAND Flash co-exist with IDE devices
• General purpose chip select pins support on-board ISA-
• Programmable timing supports a variety of Flash
• Supports up to four byte-wide NOR Flash devices.
• Supports up to four byte-wide NAND Flash devices.
• Supports four programmable chip select pins with
AMD Geode™ CS5535 Companion Device Data Book
Flash devices on IDE interface. No extra pins needed.
with PIO (Programmed I/O) only mode.
like slave devices.
devices.
— Address up to 256 KB boot ROMs using an external
— Address up to 256 MB linear Flash memory arrays
— Boot ROM capability.
— Burst mode capability (DWORD read/write on PCI
— Hardware support for SmartMedia-type ECC (Error
memory or I/O addressable.
— Up to 1 KB of address space without external latch.
octal latch.
using external latches.
bus).
Correction Code) calculation off-loading software
effort.
Flash Controller
5.18.1
To understand the functioning of the NAND Flash Control-
ler, an initialization sequence and a read sequence is pro-
vided in the following sub-sections. The NAND Flash
Controller’s registers can be mapped to memory or I/O
space. The following example is based on memory
mapped registers.
5.18.1.1 Initialization
1)
2)
5.18.1.2 Read
1)
2)
3)
Program MSR_LBAR_FLSH0 (MSR 51400010h) to
establish a base address (NAND_START) and
whether in memory or I/O space. The NAND Controller
is memory mapped in this example and always occu-
pies 4 KB of memory space.
Set the NAND timing MSRs to the appropriate values
(MSRs 5140001Bh and 5140001Ch).
Allocate a memory buffer. Start at address BAh in sys-
tem memory.
Fill the buffer with the following values:
For (i = 0; i < 11; i++), write the data in buffer [BA+i] to
memory location [NAND_START + 800h + i]. Gener-
ate the command and address phase on the NAND
Flash interface.
– BA: 02h (Assert CE#, CLE)
– BA + 1: 00h (Command: Read mode)
– BA + 2: 04h (Assert CE#, ALE, De-assert CLE)
– BA + 3: CA (Start column address)
– BA + 4: 04h
– BA + 5: PA0 (Page address byte 0)
– BA + 6: 04h
– BA + 7: PA1 (Page address byte 1)
– BA + 8: 04h
– BA + 9: PA2 (Page address byte 2)
– BA + 10: 08h (Assert CE#, De-assert ALE, Enable
Interrupt)
NAND Flash Controller
31506B
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