CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 233

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

GeodeLink™ PCI South Bridge Register Descriptions
6.2.1.5
MSR Address
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
63:50
49:48
15:7
Bit
Bit
16
6
5
4
3
2
1
0
GLD Power Management MSR (GLPCI_GLD_MSR_PM)
Name
MAR_ERR_
FLAG
RSVD
TAS_ERR_EN
PARE_ERR_EN
SYSE_ERR_EN
EXCEP_ERR_
EN
RSVD
TAR_ERR_EN
MAR_ERR_EN
Name
RSVD (RO)
IOMODEA
51000004h
R/W
00000000_00000000h
RSVD
GLPCI_GLD_MSR_ERROR Bit Descriptions (Continued)
Description
Master Abort Received Error Flag. If high, records that an ERR was generated due to
the reception of a master abort on the PCI bus. Write 1 to clear; writing 0 has no effect.
MAR_ERR_EN (bit 0) must be set to enable this event and set flag.
Reserved (Read Only). Returns 0.
Target Abort Signaled Error Enable. Write 1 to enable TAS_ERR_FLAG (bit 22) and to
allow the event to generate an ERR.
Parity Error Enable. Write 1 to enable PAR_ERR_FLAG (bit 21) and to allow the event
to generate an ERR.
System Error Enable. Write 1 to enable SYSE_ERR_FLAG (bit 20) and to allow the
event to generate an ERR.
Exception Bit Error Enable. Write 1 to enable EXCEP_ERR_FLAG (bit 19) and to allow
the event to generate an ERR.
Reserved (Read Only). Returns 0.
Target Abort Received Error Enable. Write 1 to enable TAR_ERR_FLAG (bit 17) and to
allow the event to generate an ERR.
Master Abort Received Enable. Write 1 to enable MAR_ERR_FLAG (bit 16) and to
allow the event to generate an ERR.
Description
Reserved (Read Only). Returns 0.
I/O Mode A Control. These bits determine how the associated PCI inputs and outputs
will behave when the PMC asserts two internal signals that are controlled by PMS I/O
Offset 20h and 0Ch. The list of affected signals is given in Table 4-11 "Sleep Driven PCI
Signals" on page 79.
00: No gating of I/O cells during a Sleep sequence (Default).
01: During a power management Sleep sequence, force inputs to their non-asserted
10: During a power management Sleep sequence, force inputs to their non-asserted
11: Immediately and unconditionally, force inputs to their not asserted state, and park
state when PM_IN_SLPCTL is enabled.
state when PM_IN_SLPCTL is enabled, and park (force) outputs low when
PM_OUT_SLPCTL is enabled.
(force) outputs low.
GLPCI_GLD_MSR_PM Bit Descriptions
CLPCI_GLD_MSR_PM Register Map
RSVD
MODEA
IO
9
RSVD
8
31506B
7
6
MODE2
5
P
4
MODE1
3
P
2
MODE0
1
P
233
0