CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 335

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Diverse Integration Logic Register Descriptions
6.6.2.11 Ball Options Control (DIVIL_BALL_OPTS)
MSR Address
Type
Reset Value
AMD Geode™ CS5535 Companion Device Data Book
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
22:20
18:16
15:2
Bit
23
19
1
0
Name
RSVD
UART2_ENABLE
[2:0]
RSVD
UART1_ENABLE
[2:0]
RSVD
RTC_ENABLE1
RTC_ENABLE0
51400015h
R/W
00000x7xh
Description
Reserved. Reads return value written. Defaults to 0.
UART2 Enable.
0xx: UART2 not enabled into DIVIL I/O space; use LPC.
100: UART2 enabled into I/O base 02E8h (COM4).
101: UART2 enabled into I/O base 02F8h (COM3).
110: UART2 enabled into I/O base 03E8h (COM2).
111: UART2 enabled into I/O base 03F8h (COM1).
If UART1 and UART2 are set to the same I/O base, a decode error is generated on
access.
Reserved. Reads return value written. Defaults to 0
UART1 Enable.
0xx: UART1 not enabled into DIVIL I/O space; use LPC.
100: UART1 enabled into I/O base 02E8h (COM4).
101: UART1 enabled into I/O base 02F8h (COM3).
110: UART1 enabled into I/O base 03E8h (COM2).
111: UART1 enabled into I/O base 03F8h (COM1).
If UART1 and UART2 are set to the same I/O base, a decode error is generated on
access.
Reserved. Reads return value written. Defaults to 0
Real-Time Clock Map 1. Routes I/O port locations 072h and 073h to the internal RTC
high RAM or LPC.
0: RTC high RAM routed to LPC bus.
1: RTC high RAM routed to internal RTC. (Default)
Real-Time Clock Map 0. Routes I/O port locations 070h and 071h internal RTC or
LPC. Writes to port 070h (Index) are always routed internal. The MSB is used to estab-
lish the NMI enable state.
0: RTC routed to LPC bus.
1: RTC routed to internal RTC. (Default)
RSVD
DIVIL_LEG_IO Bit Description (Continued)
DIVIL_BALL_OPTS Register Map
9
8
31506B
7
6
5
4
3
2
1
335
0