CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 401

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

UART and IR Port Register Descriptions
AMD Geode™ CS5535 Companion Device Data Book
Bit
4
3
2
1
0
Name
LOOP
DMASWP
DMATH
DMANF
EXT_SL
Description
Loopback Enable. During loopback, the transmitter output is connected internally to the
receiver input, to enable system self-test of serial communication. In addition to the data
signal, all additional signals within the UART are interconnected to enable real transmis-
sion and reception using the UART mechanisms. When this bit is set to 1, loopback is
selected. This bit accesses the same internal register as bit 4 in the MCR, when the
UART is in a non-extended mode. Loopback behaves similarly in both non-extended and
extended modes. When extended mode is selected, the DTR bit of the MCR internally
drives both DSR and RI, and the RTS bit drives CTS and DCD.
During loopback, the following occurs:
• The transmitter and receiver interrupts are fully operational. The modem status inter-
• The DMA control signals are fully operational.
• UART and IR receiver serial input signals are disconnected. The internal receiver input
• The UART transmitter serial output is forced high and the IR transmitter serial output is
• The virtual modem signals of MSR_UART[x]_MOD register (DSR, CTS, RI and DCD)
DMA Swap. This bit selects the routing of the DMA control signals between the internal
DMA logic and configuration module of the chip. When this bit is 0, the transmitter and
receiver DMA control signals are not swapped. When it is 1, they are swapped. A block
diagram illustrating the control signals routing is shown in Figure 6-2 "DMA Control Sig-
nals Routing" on page 402. The swap feature is particularly useful when only one 8237
DMA channel is used to serve both transmitter and receiver. In this case, only one exter-
nal DMA Request/DMA Acknowledge pair is interconnected to the swap logic by the con-
figuration module. Routing the external DMA channel to either the transmitter or receiver
DMA logic is then controlled by the DMASWP bit. This way, the IR device drivers do not
need to know the details of the configuration module.
DMA FIFO Threshold. This bit selects the TX_FIFO and RX_FIFO threshold levels used
by the DMA request logic to support demand transfer mode. A transmission DMA request
is generated when the TX_FIFO level is below the threshold. A reception DMA request is
generated when the RX_FIFO level reaches the threshold or when an RX_FIFO timeout
occurs. Table 6-40 lists the threshold levels for each FIFO.
DMA Fairness Control. This bit controls the maximum duration of DMA burst transfers.
0: DMA requests forced inactive after approximately 10.5 µs of continuous transmitter
1: TX-DMA request is deactivated when the TX_FIFO is full. An RX DMA request is
Extended Mode Select. When set to 1, extended mode is selected.
rupts are also fully operational, but the interrupt sources are now the lower bits of the
MCR. Modem interrupts in IR modes are disabled unless the IRMSSL bit of the IRCR2
is 0. Individual interrupts are still controlled by the IER bits.
signals are connected to the corresponding internal transmitter output signals.
forced low, unless the ETDLBK bit is set to 1, in which case they function normally.
are disconnected. The internal modem status signals are driven by the lower bits of
the MCR.
and/or receiver DMA operation (default).
deactivated when the RX_FIFO is empty.
EXCR1 Bit Descriptions (Continued)
31506B
401