CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 114

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CS5535-UDCF

Manufacturer Part Number
CS5535-UDCF
Description
Manufacturer
AMD (ADVANCED MICRO DEVICES)
Datasheet

Specifications of CS5535-UDCF

Operating Temperature (min)
0C
Operating Temperature (max)
85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
CS5535-UDCF
Manufacturer:
AMD
Quantity:
20 000
5.8.2
For each of 16 input IGs of four signals each (except IG0
and IG2 with two signals each), XPIC provides a four input
“OR”. Thus, 16 outputs are formed. A software readable
XPIC Input Request Register (XIRR) is available to read
the status of the 64 inputs. Outputs [0:1] and [3:15] are
connected directly to the corresponding inputs on LPIC.
Output 2 can be used as an ASMI.
5.8.3
The LPIC consists of two 8259A compatible Programmable
Interrupt Controllers (PICs) connected in Cascade mode
through IR2 (see Figure 5-19). The LPIC devices support
all x86 modes of operation except Special Fully Nested
mode. LPIC contains mechanisms to:
1)
114
Note:
Mask any of the 15 inputs via an Interrupt Mask Regis-
ter (IMR).
Extended PIC (XPIC)
Legacy PIC (LPIC)
Cascading the 8259A PICs. The INT output of the slave is connected to the IRQ2 input of the master.
IRQ8
31506B
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
IRQ9
D0-D7
IRQ10
8259A Slave
IRQ11
Figure 5-19. Cascading 8259As for LPIC
IRQ12
IRQ13
INTA
IRQ14
INT
IRQ15
2)
3)
4)
5)
In addition to the above 8259A features, there are two reg-
isters to control edge/level mode for each of the interrupt
inputs as well as shadow registers to obtain the values of
legacy 8259A registers that have not been historically
readable.
Determine the input request status via an Interrupt
Request Register (IRR).
Generate an interrupt request (INTR) to the processor
when any of the unmasked requests are asserted.
Provide an interrupt vector to the processor as part of
an interrupt acknowledge operation based on request
priorities.
Determine which requests are acknowledged but not
yet fully serviced, via an In-Service Register (ISR).
AMD Geode™ CS5535 Companion Device Data Book
IRQ0
IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
IRQ1
D0-D7
IRQ2
8259A Master
IRQ3
Programmable Interrupt Control
IRQ4
IRQ5
INTA
IRQ6
INT
IRQ7

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