CS5535-UDCF AMD (ADVANCED MICRO DEVICES), CS5535-UDCF Datasheet - Page 360

• Manufacturer Part Number: CS5535-UDCF
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of CS5535-UDCF

• Operating Temperature (min): 0C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

6.9.2.8
I/O Port
Type
Reset Value
360
Bit
6:5
4:3
1:0
RSVD
7
2
7
Operation Command Word 3 (PIC_OCW3)
Name
RSVD
SP_MASK
01
RSVD
REG_READ
Master: 020h
Slave:
6
31506B
SP_MASK
0A0h
WO
00h
Description
Reserved. Write to 0.
Special Mask Mode. The internal SMM bit can be set or cleared using this 2-bit field.
0x: No change to the internal SMM bit.
10: Clears the internal SMM bit (i.e., value of SMM bit = 0). (Default after initialization.)
11: Sets the internal SMM bit (i.e., value of SMM bit = 1).
While the internal SMM bit is 1, interrupt blocking by priority is disabled, and only the
Interrupt Mask Register (OCW1) is used to block interrupt requests to the CPU. While
the internal SMM bit is 0 (the default), an unmasked IRQ must also be of higher priority
than the IRQ of the currently running interrupt service routine. Regardless of the setting
of this bit, the IRQ priority is still used to arbitrate among multiple allowed IRQ requests
at the time of an Interrupt Acknowledge access from the CPU.
Write to 01. Write to 01 to write OCW3 (rather than OCW2 or ICW1). (See Section
6.9.2 "PIC Native Registers" on page 356.)
Reserved. Write to 0. (Poll Command at this address is not supported.)
Register Read Mode.
00: No operation.
10: Read interrupt request register on next read of I/O Port 020h (master) or 0A0h
01: No operation.
11: Read interrupt service register on next read of I/O Port 020h (master) or 0A0h
5
(slave).
(slave).
PIC_OCW3 Bit Descriptions
PIC_OCW3 Register Map
4
01
Programmable Interrupt Controller Register Descriptions
3
AMD Geode™ CS5535 Companion Device Data Book
RSVD
2
1
REG_READ
0